比较有意义资料

Education .ppt

User-guide

Coherent Accelerator Interface Architecture.pdf

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CAPI (coherent accelerator …)

首先是 accelerator，然后是coherent，区分于基于I/O的accelerator

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看了CAPI 的education，写得详细，大致知道了流程，

遗留问题是WED的数据结构。。。。

1)     App Connect to accelerator-> Open Device ->PSL Reset AFU (通过control interface) |    AFU ready

              if ((afu_handle = cxl_afu_open_dev(“/dev/cxl/afu0.0”)) < 0) {

 

1.1) See if there’s an FPGA available

num_accel = accel_get_info(FPGA_ACCEL,ACCEL_COUNT_PHYSICAL_ACCEL,-1);

1.2) See if there are Slices available on the fpga

num_Slices = accel_get_info(FPGA_ACCEL,ACCEL_COUNT_HWSLICES,-1);

1.3) Create fpga slice and download

app_handle = create_and_open_dev(“/dev/capia1m”,”capi”,1);

2）  App set data structure (应该是WED list)

3）  App Start accelerator - >  Attach Device -> PSL_WED_Ax set to AddrX CNTL_Reg set(通过control interface) | AFU starts with WED location

if ( cxl_afu_attach( afu_handle, myWED_ptr, -1, 0 ) < 0 ) {   注意此时把WED和AFU联系起来！

4)     MMIO访问

5)     app访问problem state area

afu_ps_area = mmap( NULL, SIZE, PROT_READ|PROT_WRITE, MAP_SHARED, afu_fd, 0 );

6)    干完后munmap( afu_ps_area, SIZE );

           cxl_afu_free( afu_handle );

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PSL和AFU之间5个interface

其信号命名和interface有关

c: commande interface

b: buffer interface

r: response interface

mm: MMIO interface

j: control interface (job management)

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afu干活的流程  （注意PSL才是master，所有动作由其完成，这样便于coherent！！！）

1)     PSL 通过control interface写入WED

2)     AFU 通过accelerator command interface去invoke  PSL的service,带上tag标志（

比如：Accelerator is using command code 0x0A60 – Read_cl_m to indicate the data should be cached in the PSL）

3)     PSL 去完成这个service，AFU是读，其实PSL就是写操作(from PSL to AFU)，通过accelerator buffer interface。对应AFU invoke的tag标志

4)     完成后，PSL通过PSL RESPONSE interface，告知AFU完成了这个AFU的invoke 的service